1. Field of the Invention
This invention relates generally to the area of bit synchronizing to data transmissions received by a data receiver. Particularly this invention relates to a digital phase locked loop bit synchronizer for use in a portable paging receiver.
2. Description of the Prior Art
Bit synchronization to a digital transmission is a process used to determine bit boundaries of a data transmission and thereafter to synchronously sample bits of data from the data transmission. Bit synchronization may be used in a paging receiver which decodes a digital signaling protocol proposed by British Telecom in England which is commonly termed POCSAG (Post Office Code Standardization Advisory Group).
Synchronization to this protocol is known and has been described in detail in U.S. Pat. No. 4,518,961, May 21, 1985, to Davis et al. which shows synchronization to either the POCSAG or a Golay signalling protocols. Additionally, U.S. Pat. No. 4,506,262, Mar. 19, 1985 to Vance et al. shows synchronization to POCSAG using an early/late phase locked loop with coarse and fine synchronization modes.
Line 10 of FIG. 1 shows a typical POCSAG signal. Prior to the signal, noise or another type of protocol may be transmitted as shown in area 12 enclosed in a broken line. The POCSAG signal begins with a preamble signal, 14, which consists of a number of one-zero transitions. The preamble is followed by a plurality of thirty two bit information words, each coded in a 31,21 extended BCH code (32,21). The information words begin with a sync code word 16a which contains predetermined binary sequence. Every seventeenth word thereafter another sync code, 16b, occurs in the signal. Between sync codes, the information is structured as 8 information frames each of which contain two (32,21) words. For illustration, the contents of frame 4, as indicated by numeral 18, is shown on line 34. Line 34 has two 32 bit words, 36 and 38, each information word having 32 data bits structured in the (32,21) format. It can be appreciated that when viewed as an unsynchronized data signal, the bit sequence shown on line 34 appears to be a random bit sequence.
The sync code provides a means for frame synchronization to the signal. Thus it is desirable to first bit synchronize to the preamble signal and subsequently frame synchronize to the sync code. Line 20 shows the operation of a pager synchronizing to the POCSAG signal. During interval 22 and 24, the pager is attempting to synchronize to the signal. However, the signal is not present. During interval 26, the preamble signal, 14, is present, the pager bit synchronizes and finds sync code 16a. Then in a known manner, the pager decodes information in preassigned frame 4 as shown by intervals 28 and 32. The pager also tests for sync code 16b during interval 30.
In some instances, the preamble signal may be corrupted by noise rendering the the preamble signal undetectable. In this situation, it is desirable to acquire bit synchronization on the data bits within the thirty two bit words, and subsequently frame synchronize to one of the periodic sync code signals 16b. The bit synchronization process in this mode is more difficult because the data in the thirty two bit words is effectively random. Consequently, it is desirable to provide a selective call receiver capable of acquiring bit synchronization on either a POCSAG preamble signal or data signals within POCSAG information words.
The POCSAG protocol may be transmitted at one of two data rates, 512 bits per second, or 1200 bits per second. It would be very desirable to selected the data rate at which a paging receiver operates at the point of sale. This selection may be jumper selected or programmed into the pager code plug. Consequently, it is desirable to provide a selective call receiver having a phase locked loop clocked by a single frequency which may be configured to operate at either data rate. Additionally, to provide for substantially identical operating characteristics at both data rates, it is desirable to maintain a constant bandwidth to data rate ratio of the phase locked loop at both data rates.
Finally, in order to compete in the paging market, is desirable to produce paging receivers at a low cost. A low cost may be achieved by having a minimum number of component parts within the paging receiver. Thus it is desirable to construct the phase locked loop entirely on a single integrated circuit and clocked with a frequency generated with a single crystal while being able to synchronize at either data rate.